1. Field of the Invention
The present invention concerns a nonvolatile semiconductor memory and, more particularly, the structure of a NOR-type flash electrically erasable and programmable read-only memory (EEPROM).
2. Description of the Related Art
Nonvolatile semiconductor memory is typically used in applications for Mask ROM, EPROM, EEPROM, flash EEPROM, etc. Flash EEPROM features immediate electrical erasure of data and low power consumption and, therefore, is typically used as a permanent memory in devices such as a notebook computer or a memory card for a digital camera.
The logical state of the data stored in a nonvolatile semiconductor memory cell is determined by the threshold voltage of the cell transistor. The threshold voltage is defined as the voltage required between the control gate and the source of the cell transistor in order to turn on the transistor. Each cell transistor of an EPROM, EEPROM or flash EEPROM has a floating gate that is isolated from the control gate. The threshold voltage of each cell transistor varies with the amount of charge stored on the floating gate. Thus, data is stored or programmed by increasing or decreasing the amount of charge on the floating gate.
In order to read out data from a programmed cell, the decoder circuit is employed to apply a voltage signal to the cell and the related circuit in order to obtain a current or voltage signal on a bit line for the cell. The current or voltage signal on the bit line represents the data stored in the cell. A sense amplifier connected to the bit line is used to detect the current or voltage signal and identify the data as a logical "1" or "0".
The structure of the memory cell array is largely classified into NOR-type and NAND-type according to the manner in which the memory cells are connected to the bit lines. A NOR-type structure has each memory cell connected between the bit line and the source line. A NAND-type structure has a string of memory cells connected in series between the bit line and a ground line.
The NOR-type structure is inferior to the NAND-type in view of the scale of integration that can be achieved. However, the NOR-type structure obtains higher operational speed due to higher cell current. Consequently, the NOR-type structure has tended to supplant the NAND-type and the focus of development has been on seeking improvement of the scale of integration of the NOR-type cell transistors.
An example of a NOR-type flash EEPROM is disclosed in an article entitled "A Single Transistor EEPROM Cell and Its Implementation in a 512K CMOS EEPROM" authored by Satyen Mukherjee et al, IEDM, pp. 616-619, 1985. This structure has each bit line commonly connected with two cell transistors. The source region of each of the two cell transistors is extended and connected with a common source line. This requires a bit line contact for the two cell transistors which limit the scale of integration that can be achieved.
In addition, electrical resistance increases with the length of the source region that is extended to the common source line. The increased source resistance of the cell transistors can cause a read or program operation on the cell to fail. Such an operational failure can be prevented by decreasing the interval between the source region and the common source line and by providing a common bit line in place of several bit lines. But the extent of the common source lines makes it difficult to improve the scale of integration of the memory cells.